
2004 Microchip Technology Inc.
DS30491C-page 303
PIC18F6585/8585/6680/8680
REGISTER 23-32: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN RECEIVE MODE
[0
≤ n ≤ 5, 0 ≤ m ≤ 7, TXnEN (BSEL<n>) = 0](1)
REGISTER 23-33: BnDm: TX/RX BUFFER n DATA FIELD BYTE m REGISTERS IN TRANSMIT MODE
[0
≤ n ≤ 5, 0 ≤ m ≤ 7, TXnEN (BSEL<n>) = 1](1)
R-xR-x
BnDm7
BnDm6
BnDm5
BnDm4
BnDm3
BnDm2
BnDm1
BnDm0
bit 7
bit 0
bit 7-0
BnDm7:BnDm0: Receive Buffer n Data Field Byte m bits (where 0
≤ n < 3 and 0 < m < 8)
Each receive buffer has an array of registers. For example, Receive Buffer 0 has 7 registers:
B0D0 to B0D7.
Note 1: These registers are available in Mode 1 and 2 only.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
R/W-x
BnDm7
BnDm6
BnDm5
BnDm4
BnDm3
BnDm2
BnDm1
BnDm0
bit 7
bit 0
bit 7-0
BnDm7:BnDm0: Transmit Buffer n Data Field Byte m bits (where 0
≤ n < 3 and 0 < m < 8)
Each transmit buffer has an array of registers. For example, Transmit Buffer 0 has 7 registers:
TXB0D0 to TXB0D7.
Note 1: These registers are available in Mode 1 and 2 only.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown